View ES4318_182560.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ES4318 DVD Processor Product Brief
DESCRIPTION
The ES4318 Digital Video Disc (DVD) processor is a single-chip solution for a DVD player that integrates MPEG video decoding, DVD system navigation, Content Scrambling System (CSS), and DolbyTM Digital (AC-3) and MPEG audio decoding. The fully programmable ES4318 is based on a proprietary ESS architecture. It offers the best feature set in comparison to any currently existing DVD chip, and a glueless interface to various peripheral components. The ES4318 is the most cost effective solution in its class with an integration level and quality that set new benchmarks. The ES4318 processor is capable of decoding DolbyTM Digital (AC-3) or DTS digital surround, simultaneously with MPEG-1 or MPEG-2 video. For embedded applications, the ES4318's internal RISC processor can be used in place of a microcontroller to provide all system control, DVD system navigation, CSS decryption, and many other features. On-chip, multi-tap filters provide arbitrary scaling with state of the art SmartScaleTM technology useful for video standards conversion. SmartStreamTM technology from ESS provides video error concealment and video post-processing, leading to the highest playability and video quality. Other features included in the ES4318 are video letterbox display, DVD Sub-Picture overlay, and On-Screen Display. The ES4318 provides a glueless 8/16-bit parallel interface to most DVD servo/loaders. It connects directly with 8/16-bit ROM and 16-bit SDRAM/EDO. An 8-bit YUV video interface supports many TV encoders. General purpose auxiliary pins are provided to control various peripheral devices. A standard I2S interface supports popular audio DACs and ADCs. The ES4318 also features a direct S/PDIF output. A block diagram of a typical stand-alone system using the ES4318 with the glueless SDRAM interface appears below. The DVD system stream from a DVD disc is passed to the ES4318 through the 8-bit/16-bit parallel host interface. The ES4318 parses the system layer and demultiplexes the audio and video streams. Audio is decoded and passed through the I2S audio serial bus to an external audio DAC and then to the speakers. Video is decoded and output as YUV pixels to an NTSC or PAL video encoder. System control and housekeeping functions (keypad and remote control) are also provided on-chip.
FEATURES
* Single-chip DVD video decoder in a 208-pin PQFP package * MPEG-1 system and MPEG-2 program streams parsing
supported
* Programmable multimedia processor architecture * Compatible with Audio CD, VideoCD, VCD 3.0, and Super
VideoCD (SVCD)
* DVD Navigation 1 * Built-in Content Scrambling System (CSS) circuitry
Video
* Pan & Scan and Letter-Box conversions * Trick modes include Slow, Fast Forward, Fast Reverse, Step,
and Goto
* Sub-Picture decoder supports karaoke/subtitling functions * 4-bit On-Screen Display (OSD) with 4-bit blending * 8-bit YUV component video output
Audio
* * * * * * * *
Built-in Karaoke key-shift function DolbyTM Digital 2-channel downmix audio output for DolbyTM Dolby Pro Logic Linear PCM streams for 24 bit/96KHz Concurrent S/PDIF out and 2-channel audio output Sensaura Dolby Digital Virtual Suround DTS Digital Surround 2-channel downmix stereo output S/PDIF output for encoded AC-3, DTS Digital output or Linear PCM Glueless interface to DVD loaders (ATAPI or A/V bus I/F) Bidirectional I2S audio interface Direct servo/loader interface 8 general-purpose auxiliary ports Single 27 MHz clock input
Peripheral
* * * * *
Smart Technology
* SmartZoomTM for motion zoom and pan * SmartScaleTM for NTSC to PAL conversion and vice versa * SmartStreamTM for video error concealment; supports
Microsoft WindowsTM Sound System(R)
BLOCK DIAGRAM
EPROM Video NTSC/PAL Encoder Audio CODEC Panel Interface TV MIC Speakers Remote Control/ Keypad
DVD drive
Audio ES4318
2MByte SDRAM
ESS Technology, Inc.
SAM0377-052101
1
ES4318 PRODUCT BRIEF
PINOUT
VSS HA1 HA0 HCS3FX# HCS1FX# HIOCS16# HRD#/DCI_ACK# HWR#/DCI_CLK VCC VSS HIORDY HRST# HIRQ/DCI_ERR# HRDQ# HWRQ#/DCI_REQ# HD15 HD14 VCC VSS HD13 HD12 HD11 HD10 HD9 HD8/DCI_FDS# HD7/DCI7 VCC VSS HD6/DCI6 HD5/DCI5 HD4/DCI4 HD3/DCI3 HD2/DCI2 HD1/DCI1 HD0/DCI0 VCC VSS HSYNCH# VSYNCH# PCLKQSCN PCLK2XSCN YUV7 YUV6 YUV5 VSS VCC YUV4 YUV3 YUV2 YUV1 YUV0 DCLK VCC HA2 VPP AUX0 AUX1 AUX2 VSS VCC AUX3 AUX4 AUX5 AUX6 AUX7 LOE# VSS VCC LCS0# LCS1# LCS2# LCS3# VSS LD0 LD1 LD2 LD3 LD4 VCC VSS LD5 LD6 LD7 LD8 LD9 LD10 LD11 VSS VCC LD12 LD13 LD14 LD15 LWRLL# LWRHL# VSS VCC NC NC LA0 LA1 LA2 LA3 VSS 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
ES4318 208-Pin PQFP Package
PIN DESCRIPTION
Name VCC LA[21:0] VSS RESET# Number 1, 9, 18, 27, 35, 44, 51, 59, 68, 75, 83, 92, 99, 104, 111, 121, 130, 139, 148, 157, 164, 172, 183, 193, 201 23:19,16:10,7:2,207:204 8,17,26,34,43,52,60,67,76,84,91,98,103,112,120,129,1 38,147,156,163,171,177,184,192,200,208 24 I/O I O I I Definition 3.65 V 150 mv. Device address output. Ground. Reset input, active low.
2
SAM0377-052101
VCC LA4 LA5 LA6 LA7 LA8 LA9 VSS VCC LA10 LA11 LA12 LA13 LA14 LA15 LA16 VSS VCC LA17 LA18 LA19 LA20 LA21 RESET# TDMDX/RSEL VSS VCC TDMDR TDMCLK TDMFS TDMTSC# TWS/SEL_PLL1 TSD/SEL_PLL0 VSS VCC SEL_PLL2 NC NC MCLK TBCK SPDIF_DOBM NC VSS VCC RSD RWS RBCK APLLCAP XIN XOUT VCC VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
VCC VSS DSCK DQM DCS0# VCC VSS DCS1# DB15 DB14 DB13 DB12 VCC VSS DB11 DB10 DB9 DB8 DB7 DB6 VSS VCC DB5 DB4 DB3 DB2 DB1 DB0 VSS VCC DRAS2# DRAS1# DRAS0# DWE# DOE#/DSCK_EN DCAS# VCC VSS DMA11 DMA10 DMA9 DMA8 DMA7 DMA6 VSS VCC DMA5 DMA4 DMA3 DMA2 DMA1 DMA0
Figure 1 ES4318 Device Pinout
ESS Technology, Inc.
ES4318 PRODUCT BRIEF
Name TDMDX RSEL
Number
I/O O I
Definition TDM transmit data. ROM Select RSEL 0 1 Selection 16-bit ROM 8-bit ROM
25
TDMDR TDMCLK TDMFS TDMTSC# TWS SEL_PLL1 TSD SEL_PLL0
28 29 30 31 32
I I I O O I O I
TDM receive data. TDM clock input. TDM frame synch. TDM output enable, active low. Audio transmit frame sync. Select PLL1. Audio transmit serial data port. Select PLL0. SEL_PLL2 0 0 1 1 SEL_PLL0 0 1 0 1 Clock Output 2.5 x DCLK 3 x DCLK 3.5 x DCLK 4 x DCLK
33
SEL_PLL2 MCLK TBCK SPDIF_DOBM RSD RWS RBCK APLLCAP XIN XOUT DMA[11:0] DCAS# DOE# DSCK_EN DWE# DRAS[2:0]# DB[15:0] DCS[1:0]# DQM DSCK DCLK YUV[7:0] PCLK2XSCN PCLKQSCN VSYNCH# HSYNCH# HD[15:0] HCS1FX# HCS3FX# HIOCS16# HA[2:0] VPP HWR#/DCI_ACK# HRD#/DCI_CLK HD[15:0] HWRQ# HRDQ# HIRQ HRST# HIORDY HWR# AUX[7:0] LOE# LCS[3:0]# LD[15:0] LWRLL# LWRHL# NC
36 39 40 41 45 46 47 48 49 50 66:61,58:53 69 70 71 74:72 96:93,90:85,82:77 97,100 101 102 105 115:113,110:106 116 117 118 119 141:140,137:131,128:122 152 153 151 158, 155:154 159 149 150 141:140,137:131,128:122 142 143 144 145 146 149 169:165,162:160 170 176:173 197:194, 191:185, 182:178 198 199 37,38,42,203:202
I/O I/O O I I I I I O O O O I O O I/O O O O I O I/O I/O I/O I/O O O O I I/O I I,I I,I I/O O O I/O O I O I/O O O I/O O O
Select PLL2. See the table for pin number 33. Audio master clock for audio DAC. Audio transmit bit clock. S/PDIF (IEC958) Format Output. Audio receive serial data. Audio receive frame synch. Audio receive bit clock. Analog PLL Capacitor. Crystal input. Crystal output. DRAM address bus. Column address strobe, active low. Output enable, active low. Clock Enable, active low. DRAM write enable, active low. Row address strobe, active low. DRAM data bus. SDRAM chip select [1:0], active low. Data input/output mask. Clock to SDRAM. Clock Input (27 MHz) 8-bit YUV output. 2X pixel clock. Pixel clock. Vertical sync for screen video interface, programmable for rising or falling edge, active low. Horizontal sync for screen video interface, programmable for rising or falling edge, active low. Host data bus Host select 1. Host select 3. Device 16-bit data transfer. Host address bus. Peripheral protection voltage. Host write/DCI Interface Acknowledge Signal, active low. Host read/DCI Interface Clock. Host data bus. Host write request. Host read request. Host interrupt. Host reset. Host I/O ready. Host write request. Auxiliary ports. Device output enable, active low. Chip select [3:0], active low. Device data bus. Device write enable, active low. Device write enable, active low. No connect.
ESS Technology, Inc.
SAM0377-052101
3
ES4318 PRODUCT BRIEF
ORDERING INFORMATION
Part Number ES4318 Description DVD Processor
D D1 D3
156 105
Package 208-pin TQFP
MECHANICAL DIMENSIONS
157
104
Note: 1. All dimensions are in inches (millimeter). 2. Actual package used has millimeter native dimensions - take care with rounding from metric to imperial.
Symbol A
E3 E1 E
Min - 0.010 (0.25) 0.130 (3.30) 0.007 (0.18) 0.005 (0.12) 1.195 (30.35) 1.098 (27.90)
Nom - - 0.134 (3.40) 0.009 (0.23) 0.006 (0.16) 1.205 (30.60) 1.102 (28.00)
Max 0.165 - 0.138 (3.50) 0.011 (0.28) 0.008 (0.20) 1.215 (30.85) 1.106 (28.10)
A1 A2 B C
208
Index Pin 1 1 52
53
D D1
A
D3 e
e
1.004 (25.50) REF 0.0197 (0.50) BASIC 1.195 (30.35) 1.098 (27.90) 1.205 (30.60) 1.102 (28.00) 1.215 (30.85) 1.106 (28.10)
see detail
E E1
A2 A1
B
L
C
No part of this publication may be reproduced, stored in a retrieval system, transmitted, or translated in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without the prior written permission of ESS Technology, Inc. ESS Technology, Inc. makes no representations or warranties regarding the content of this document. All specifications are subject to change without prior notice.
ESS Technology, Inc. assumes no responsibility for any errors contained herein. (P) U.S. Patent 4,214,125 and others, other patents pending. VideoDriveTM is a trademark of ESS Technology, Inc. MPEG is the Moving Picture Experts Group of the ISO/ IEC. All other trademarks are owned by their respective holders and are used for identification purposes only.
4
(c) 2000--2001 ESS Technology, Inc. All rights reserved.
SAM0377-052101

▲Up To Search▲

Price & Availability of ES4318

	To Download ES4318 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .